Low Power Active Inductor Using Symmetrical Structure
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- Sato Takahide
- University of Yamanashi
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- Takagi Shigetaka
- Tokyo Institute of Technology
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- Fujii Nobuo
- Tokyo Institute of Technology
Bibliographic Information
- Other Title
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- アクティブインダクタの対称構成による低消費電力化
- アクティブインダクタ ノ タイショウ コウセイ ニ ヨル テイショウヒ デンリョクカ
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Abstract
This paper proposes power-consumption and chip-area reduction technique for OTA-C based active inductors. In the proposed technique a conventional floating active inductor is divided into two identical active inductors whose chip-size and power consumption are half of the original one. The two divided active inductors are connected in parallel. In the parallel connection opposite ends of the two divided active inductors are connected. Thanks to this modification two pairs of OTAs can be merged and the total number of OTAs is minimized. The proposed technique ideally achieves 33 % reduction in power consumption and more than 33 % reduction in chip-area of the conventional active inductor. Moreover, the proposed active inductor has low mismatch characteristics because it is perfectly symmetrical. It is also shown that the proposed technique is vely effective in low power design of a pair of active inductors for fully balanced circuits.
Journal
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- IEEJ Transactions on Electronics, Information and Systems
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IEEJ Transactions on Electronics, Information and Systems 129 (8), 1534-1540, 2009
The Institute of Electrical Engineers of Japan
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Details 詳細情報について
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- CRID
- 1390282679580503040
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- NII Article ID
- 10025101676
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- NII Book ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL BIB ID
- 10395934
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed