A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

DOI Web Site 被引用文献2件 参考文献19件
  • YAO Jun
    Graduate School of Informatics, Kyoto University The Institute of Electronics, Information and Communication Engineers
  • MIWA Shinobu
    Graduate School of Engineering, Tokyo University of Agriculture and Technology The Institute of Electronics, Information and Communication Engineers
  • SHIMADA Hajime
    Graduate School of Informatics, Kyoto University The Institute of Electronics, Information and Communication Engineers
  • TOMITA Shinji
    Graduate School of Informatics, Kyoto University The Institute of Electronics, Information and Communication Engineers

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Recently, a method called pipeline stage unification (PSU) has been proposed to reduce energy consumption for mobile processors via inactivating and bypassing some of the pipeline registers and thus adopt shallow pipelines. It is designed to be an energy efficient method especially for the processors under future process technologies. In this paper, we present a mechanism for the PSU controller which can dynamically predict a suitable configuration based on the program phase detection. Our results show that the designed predictor can achieve a PSU degree prediction accuracy of 84.0%, averaged from the SPEC CPU2000 integer benchmarks. With this dynamic control mechanism, we can obtain 11.4% Energy-Delay-Product (EDP) reduction in the processor that adopts a PSU pipeline, compared to the baseline processor, even after the application of complex clock gating.

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