A Dependable SRAM with 7T/14T Memory Cells

• FUJIWARA Hidehiro

  Kobe University

• OKUMURA Shunsuke

  Kobe University

• IGUCHI Yusuke

  Kobe University

• NOGUCHI Hiroki

  Kobe University

• KAWAGUCHI Hiroshi

  Kobe University

• YOSHIMOTO Masahiko

  Kobe University JST, CREST

Abstract

This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21V and 0.26V, respectively, with a bit error rate of 10^-8 kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E92-C (4), 423-432, 2009

  The Institute of Electronics, Information and Communication Engineers

Keywords

• SRAM
• dependability
• quality of a bit

Details

• CRID: 1390001204374664576
• NII Article ID: 10026821541
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e92.c.423
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E92.C/4/E92.C_4_423/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed