Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment

• KUNITAKE Yuji

  Kyushu University

• MIMA Kazuhiro

  Kyushu Institute of Technology

• SATO Toshinori

  Kyushu University Fukuoka University

• YASUURA Hiroto

  Kyushu University

抄録

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E92-C (4), 483-491, 2009

  一般社団法人 電子情報通信学会

キーワード

• worst-case design
• timing error
• co-simulation
• parameter variation

詳細情報

• CRID: 1390282679351361536
• NII論文ID: 10026821649
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e92.c.483
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E92.C/4/E92.C_4_483/_pdf
• 本文言語コード: en
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