Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism

• ENDOH Tetsuo

  CIR Tohoku University

• NORIFUSA Yuto

  CIR Tohoku University

抄録

In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20nm to 4nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10nm generation.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E92-C (5), 594-597, 2009

  一般社団法人 電子情報通信学会

キーワード

• Vertical MOSFET
• sub-10nm
• driving current
• cutoff leakage current
• current density

詳細情報

• CRID: 1390282679351440000
• NII論文ID: 10026821868
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e92.c.594
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E92.C/5/E92.C_5_594/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可