High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving

• ONIZAWA Naoya

  Research Institute of Electrical Communication, Tohoku University

• HANYU Takahiro

  Research Institute of Electrical Communication, Tohoku University

• GAUDET Vincent C.

  Department of Electrical and Computer Engineering, University of Alberta

抄録

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90nm CMOS technology, at a comparable BER.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E92-C (6), 867-874, 2009

  一般社団法人 電子情報通信学会

キーワード

• error control coding
• LDPC codes
• sum-product algorithm
• asynchronous data transfer
• multiple-valued current-mode circuit

詳細情報

• CRID: 1390282679352006400
• NII論文ID: 10026822478
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e92.c.867
• BIBCODE: 2009IEITE..92..867O
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E92.C/6/E92.C_6_867/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可