Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel

• CHOI Byung-Tae

  School of Electrical Engineering and Computer Science, Kyungpook National University

• PARK Hyung Dal

  School of Electrical Engineering and Computer Science, Kyungpook National University

• TAE Heung-Sik

  School of Electrical Engineering and Computer Science, Kyungpook National University

抄録

To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the V_t closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of V_scanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of V_scanw, also.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E92-C (11), 1347-1352, 2009

  一般社団法人 電子情報通信学会

キーワード

• wall voltage variation during address-period
• address-on-time
• <i>V_t</i> closed curves
• voltage difference between scan and address electrodes
• overlapped double scan pulse

詳細情報

• CRID: 1390001204374595456
• NII論文ID: 10026823554
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e92.c.1347
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E92.C/11/E92.C_11_1347/_pdf
• 本文言語コード: en
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