A 58-.MU.W Single-Chip Sensor Node Processor with Communication Centric Design

DOI HANDLE Web Site 参考文献26件 オープンアクセス
  • IZUMI Shintaro
    Department of Computer Science and Systems Engineering, Kobe University
  • TAKEUCHI Takashi
    Department of Computer Science and Systems Engineering, Kobe University
  • MATSUDA Takashi
    Department of Computer Science and Systems Engineering, Kobe University
  • LEE Hyeokjong
    Department of Computer Science and Systems Engineering, Kobe University
  • KONISHI Toshihiro
    Department of Computer Science and Systems Engineering, Kobe University
  • TSURUDA Koh
    Department of Computer Science and Systems Engineering, Kobe University
  • SAKAI Yasuharu
    Department of Computer Science and Systems Engineering, Kobe University
  • KAWAGUCHI Hiroshi
    Department of Computer Science and Systems Engineering, Kobe University
  • OHTA Chikara
    Department of Computer Science and Systems Engineering, Kobe University
  • YOSHIMOTO Masahiko
    Department of Computer Science and Systems Engineering, Kobe University

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This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 3 × 3mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0µW under a network environment.

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