Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET

• ENDOH Tetsuo

  Center for Interdisciplinary Research, Tohoku University

• SAKUI Koji

  Center for Interdisciplinary Research, Tohoku University

• YASUDA Yukio

  Center for Interdisciplinary Research, Tohoku University

Abstract

The excellent performance of the 10nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10nm generation.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E93-C (5), 557-562, 2010

  The Institute of Electronics, Information and Communication Engineers

Keywords

• vertical MOSFET
• 3D structured device
• MOSFET
• LSI

Details

• CRID: 1390001204376869248
• NII Article ID: 10026825411
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e93.c.557
• BIBCODE: 2010IEITE..93..557E
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E93.C/5/E93.C_5_557/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed