A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems

• LEE Jeesung

  School of Information and Communication Engineering, Inha University

• LEE Hanho

  School of Information and Communication Engineering, Inha University The Institute of Electronics, Information and Communication Engineers

抄録

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-2⁴ FFT/IFFT processor for MB-OFDM ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-2⁴ FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18μm CMOS technology in a supply voltage of 1.8V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900Msample/s at 450MHz while requiring much smaller hardware complexity and low power consumption.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A (4), 1206-1211, 2008

  一般社団法人 電子情報通信学会

キーワード

• Fast Fourier transform (FFT)
• radix-2⁴
• SDF
• multiband orthogonal frequency-division multiplexing (MB-OFDM)
• ultrawideband (UWB)

詳細情報

• CRID: 1390001206311052288
• NII論文ID: 10026848880
• NII書誌ID: AA10826239
• DOI: 10.1093/ietfec/e91-a.4.1206
• ISSN: 17451337
• ISSN: 09168508
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E91.A/4/E91.A_4_1206/_pdf
• 本文言語コード: en
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