Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits

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Author(s)

    • SATO Takashi
    • Integrated Research Institute, Tokyo Institute of Technology
    • MASU Kazuya
    • Integrated Research Institute, Tokyo Institute of Technology

Abstract

Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

Journal

  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 92(4), 1031-1038, 2009-04-01

    The Institute of Electronics, Information and Communication Engineers

References:  9

Cited by:  2

Codes

  • NII Article ID (NAID)
    10026856933
  • NII NACSIS-CAT ID (NCID)
    AA10826239
  • Text Lang
    ENG
  • Article Type
    Journal Article
  • ISSN
    09168508
  • Data Source
    CJP  CJPref  J-STAGE 
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