Statistical Gate Delay Model for Multiple Input Switching

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  • FUKUOKA Takayuki
    Department of Communications and Computer Engineering, Kyoto University
  • TSUCHIYA Akira
    Department of Communications and Computer Engineering, Kyoto University
  • ONODERA Hidetoshi
    Department of Communications and Computer Engineering, Kyoto University Photonics and Electronics Science and Engineering Center (PESEC), Kyoto University

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Abstract

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

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