The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique

• HARA Shoichi

  Department of Physical Electronics, Tokyo Institute of Technology

• MURAKAMI Rui

  Department of Physical Electronics, Tokyo Institute of Technology

• OKADA Kenichi

  Department of Physical Electronics, Tokyo Institute of Technology

• MATSUZAWA Akira

  Department of Physical Electronics, Tokyo Institute of Technology

抄録

The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -187.0dBc/Hz of FoM, can be extended from 6.5-12.5GHz to 1.5-12.5GHz. The proposed multiple-divide technique can provide a lower phase-noise, lower power consumption, smaller layout area of LC-VCO.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A (2), 424-430, 2010

  一般社団法人 電子情報通信学会

キーワード

• CMOS
• VCO
• divider
• inductor

詳細情報

• CRID: 1390282681287385856
• NII論文ID: 10026863117
• NII書誌ID: AA10826239
• DOI: 10.1587/transfun.e93.a.424
• ISSN: 17451337
• ISSN: 09168508
• Web Site: http://www.jstage.jst.go.jp/article/transfun/E93.A/2/E93.A_2_424/_pdf
• 本文言語コード: en
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