A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
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- ISHIHARA Shota
- Graduate School of Information Sciences, Tohoku University
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- IDOBATA Noriaki
- Graduate School of Information Sciences, Tohoku University
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- HARIYAMA Masanori
- Graduate School of Information Sciences, Tohoku University
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- KAMEYAMA Michitaka
- Graduate School of Information Sciences, Tohoku University
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Abstract
Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35µm-CMOS/0.60µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E93-D (8), 2134-2144, 2010
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1390282679355428480
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- NII Article ID
- 10027364639
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- NII Book ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed