A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
-
- ARAYASHIKI Yutaka
- Anritsu Devices
-
- OHKUBO Yukio
- Anritsu Devices
-
- MATSUMOTO Taisuke
- Anritsu Devices
-
- AMANO Yoshiaki
- Anritsu Devices
-
- TAKAGI Akio
- Anritsu Devices
-
- MATSUOKA Yutaka
- Anritsu Devices
この論文をさがす
抄録
We fabricated a 2: 1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120Gbit/s with a power dissipation of 1.27W and output amplitude of 520mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4W.
収録刊行物
-
- IEICE Transactions on Electronics
-
IEICE Transactions on Electronics E93-C (8), 1273-1278, 2010
一般社団法人 電子情報通信学会
- Tweet
詳細情報
-
- CRID
- 1390001204375633408
-
- NII論文ID
- 10027365882
-
- NII書誌ID
- AA10826283
-
- ISSN
- 17451353
- 09168524
-
- 本文言語コード
- en
-
- データソース種別
-
- JaLC
- Crossref
- CiNii Articles
-
- 抄録ライセンスフラグ
- 使用不可