A VGA 30fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation

• YUNBE Yoshiki

  Graduate School of Natural Science and Technology, Kanazawa University

• MIYAMA Masayuki

  Graduate School of Natural Science and Technology, Kanazawa University

• MATSUDA Yoshio

  Graduate School of Natural Science and Technology, Kanazawa University

Abstract

This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0×5.0mm² in 0.18µm process, standard cell technology. The ASIC can accommodate a VGA 30fps video with 120MHz clock frequency.

Journal

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E93-D (12), 3284-3293, 2010

  The Institute of Electronics, Information and Communication Engineers

Keywords

• affine motion model
• motion estimation
• video segmentation
• real-time processing
• VLSI
• FPGA

Details

• CRID: 1390001204377672576
• NII Article ID: 10027989064
• NII Book ID: AA10826272
• DOI: 10.1587/transinf.e93.d.3284
• ISSN: 17451361
• ISSN: 09168532
• Web Site: http://www.jstage.jst.go.jp/article/transinf/E93.D/12/E93.D_12_3284/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed