Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction

• TANAKA Yusuke

  Department of Computational Science and Engineering, Nagoya University

• ANDO Hideki

  Department of Electrical Engineering and Computer Science, Nagoya University

抄録

Two-step physical register deallocation (TSD) is an architectural scheme that enhances memory-level parallelism (MLP) by pre-executing instructions. Ideally, TSD allows exploitation of MLP under an unlimited number of physical registers, and consequently only a small register file is needed for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where either 1) pre-execution is not performed; or 2) the timing of pre-execution is delayed. Both are due to data dependencies among the pre-executed instructions. This paper proposes the use of value prediction to solve these problems. This paper proposes the use of value prediction to solve these problems. Evaluation results using the SPECfp2000 benchmark confirm that the proposed scheme with value prediction for predicting addresses achieves equivalent IPC, with a smaller register file, to the previous TSD scheme. The reduction rate of the register file size is 21%.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E93-D (12), 3294-3305, 2010

  一般社団法人 電子情報通信学会

キーワード

• microarchitecture
• microprocessor
• instruction pre-execution
• value prediction
• register file

詳細情報

• CRID: 1390282679354382976
• NII論文ID: 10027989078
• NII論文ID: 120003089189
• NII書誌ID: AA10826272
• DOI: 10.1587/transinf.e93.d.3294
• ISSN: 17451361
• ISSN: 09168532
• HANDLE: 2237/14941
• Web Site: https://nagoya.repo.nii.ac.jp/records/13046
• Web Site: http://www.jstage.jst.go.jp/article/transinf/E93.D/12/E93.D_12_3294/_pdf
• 本文言語コード: en
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