Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip

• MINAMI Ryo

  Department of Physical Electronics, Tokyo Institute of Technology

• HONG JeeYoung

  Department of Physical Electronics, Tokyo Institute of Technology

• OKADA Kenichi

  Department of Physical Electronics, Tokyo Institute of Technology

• MATSUZAWA Akira

  Department of Physical Electronics, Tokyo Institute of Technology

抄録

This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total isolation becomes less than -50dB with more than 0.4mm PA-to-LNA distance.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E94-C (6), 1057-1060, 2011

  一般社団法人 電子情報通信学会

キーワード

• CMOS
• power amplifier
• substrate coupling
• Tx leakage
• mutual coupling

詳細情報

• CRID: 1390282679351039488
• NII論文ID: 10029804335
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e94.c.1057
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E94.C/6/E94.C_6_1057/_pdf
• 本文言語コード: en
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