Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design

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著者

    • FUJIWARA Hideo
    • Graduate School of Information Science, Nara Institute of Science and Technology
    • TAMAMOTO Hideo
    • Graduate School of Engineering and Resource Science, Akita University

抄録

It is important to find an efficient design-for-testability methodology that satisfies both security and testability, although there exists an inherent contradiction between security and testability for digital circuits. In our previous work, we reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and showed a security level by clarifying the cardinality of those classes of shift register equivalents (SR-equivalents). However, SR-equivalents are not always secure for scan-based side-channel attacks. In this paper, we consider a scan-based differential-behavior attack and propose several classes of SR-equivalent scan circuits using dummy flip-flops in order to protect the scan-based differential-behavior attack. To show the security level of those SR-equivalent scan circuits, we introduce a differential-behavior equivalent relation and clarify the number of SR-equivalent scan circuits, the number of differential-behavior equivalent classes and the cardinality of those equivalent classes.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 94(7), 1430-1439, 2011-07-01

    一般社団法人 電子情報通信学会

参考文献:  22件中 1-22件 を表示

被引用文献:  3件中 1-3件 を表示

各種コード

  • NII論文ID(NAID)
    10029805571
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  CJP引用  J-STAGE 
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