Reduction of Output Conductance in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region Reduction of Output Conductance in Vertical InGaAs Channel Metal--Insulator--Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region

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In this paper, the reduction in the output conductance (g_{\text{o}}) of a vertical InGaAs channel metal--insulator--semiconductor field-effect transistor (MISFET) is reported. While vertical InGaAs channel MISFETs exhibit a high drain current density, their large g_{\text{o}} is a disadvantage. Monte Carlo simulation suggests that the large g_{\text{o}} might be caused by conduction band bending due to many space charges between the gate and drain. To prevent conduction band bending, a device in which the gate electrode overlaps with the drain region was proposed and fabricated. Consequently, g_{\text{o}} was decreased from 3.2 to 1 S/mm.

収録刊行物

  • Applied physics express

    Applied physics express 5(2), 024101-024101-3, 2012-02-25

    The Japan Society of Applied Physics

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各種コード

  • NII論文ID(NAID)
    10030155693
  • NII書誌ID(NCID)
    AA12295133
  • 本文言語コード
    EN
  • 資料種別
    SHO
  • ISSN
    18820778
  • NDL 記事登録ID
    023454417
  • NDL 請求記号
    Z78-A526
  • データ提供元
    CJP書誌  CJP引用  NDL  JSAP 
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