A 4Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement

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This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13µm CMOS technology, and the compensation range of equalization is up to 26dB at 2GHz. The test chip is verified for a 40 inch FR4 trace and a 53cm flexible printed circuit channel. The receiver occupies an area of 440µm × 520µm and has a power dissipation of 49mW (excluding the I/O buffers) from a 1.2V supply.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 94(11), 1779-1786, 2011-11-01

    The Institute of Electronics, Information and Communication Engineers

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各種コード

  • NII論文ID(NAID)
    10030190246
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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