A 1V 200kS/s 10-bit Successive Approximation ADC for a Sensor Interface

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著者

    • EO Ji-Hun
    • Analog Integrated Circuit Lab., School of Electronic Engineering, Kumoh National Instisute of Technology
    • KIM Sang-Hun
    • Analog Integrated Circuit Lab., School of Electronic Engineering, Kumoh National Instisute of Technology
    • JANG Young-Chan
    • Analog Integrated Circuit Lab., School of Electronic Engineering, Kumoh National Instisute of Technology

抄録

A 200kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43dB for a 99.01kHz analog input signal at a sampling rate of 200kS/s. The power consumption and core area are 5µW and 0.126mm<sup>2</sup>, respectively. The FoM is 47fJ/conversion-step.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 94(11), 1798-1801, 2011-11-01

    一般社団法人 電子情報通信学会

参考文献:  6件中 1-6件 を表示

被引用文献:  1件中 1-1件 を表示

各種コード

  • NII論文ID(NAID)
    10030190283
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    SHO
  • ISSN
    09168524
  • データ提供元
    CJP書誌  CJP引用  J-STAGE 
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