Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

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This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 94(10), 1948-1953, 2011-10-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030191092
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168508
  • データ提供元
    CJP書誌  J-STAGE 
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