Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications

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著者

    • JUNG Kisun
    • School of Information and Communication Engineering, Inha University
    • LEE Hanho
    • School of Information and Communication Engineering, Inha University

抄録

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/2<sup>2</sup>/2<sup>3</sup>/2<sup>4</sup> FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 94(11), 2376-2383, 2011-11-01

    The Institute of Electronics, Information and Communication Engineers

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各種コード

  • NII論文ID(NAID)
    10030192073
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168508
  • データ提供元
    CJP書誌  J-STAGE 
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