Wire Planning for Electromigration and Interference Avoidance in Analog Circuits

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著者

    • HUANG Hsin-Hsiung
    • Department of Electronic Engineering, Lunghwa University of Science and Technology
    • HUNG Jui-Hung
    • Institute of Electronic Engineering, Chung Yuan Christian University
    • LIN Cheng-Chiang
    • Department of Information and Computer Engineering, Chung Yuan Christian University
    • HSIEH Tsai-Ming
    • Department of Information and Computer Engineering, Chung Yuan Christian University

抄録

This study formulates and solves the wire planning problem with electro-migration and interference using an effective integer linear programming (ILP)-based approach. For circuits without obstacles, the proposed approach obtains a wire planning with the minimum wiring area. An effective approach for estimating the length of feasible routing wire is proposed to handle circuits with obstacles. In addition, the space reservation technique, which allocates the ring of the free silicon space around obstacles, is presented to improve interference among routing wires and on-obstacle wires. For circuits with obstacles, the proposed method minimizes total wiring area and reduces interference. Experimental results show that the integer linear-programming-based approach effectively and efficiently minimizes wiring area of routing wires.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 94(11), 2402-2411, 2011-11-01

    一般社団法人 電子情報通信学会

参考文献:  40件中 1-40件 を表示

各種コード

  • NII論文ID(NAID)
    10030192130
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168508
  • データ提供元
    CJP書誌  J-STAGE 
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