Adaptive Interference Mitigation for Multilevel Flash Memory Devices

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抄録

NAND multilevel cell flash memory devices are gaining popularity because they can increase the memory capacity by storing two or more bits to a single cell. However, when the number of levels of a cell increases, the inter-cell interference which shifts threshold voltage becomes more critical. There are two approaches to alleviate the errors caused by the voltage shift. One is the error correcting codes, and the other is the signal processing methods. In this paper, we focus on signal processing methods to reduce the inter-cell interference which causes the voltage shift, and propose two algorithms which reduce the voltage shift effects by adjusting read voltages. The simulation results show that the proposed algorithms are effective for interference mitigation.

収録刊行物

  • IEICE transactions on fundamentals of electronics, communications and computer sciences

    IEICE transactions on fundamentals of electronics, communications and computer sciences 94(11), 2453-2457, 2011-11-01

    一般社団法人 電子情報通信学会

参考文献:  8件中 1-8件 を表示

各種コード

  • NII論文ID(NAID)
    10030192286
  • NII書誌ID(NCID)
    AA10826239
  • 本文言語コード
    ENG
  • 資料種別
    SHO
  • ISSN
    09168508
  • データ提供元
    CJP書誌  J-STAGE 
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