A Self-Timed SRAM Design for Average-Case Performance

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著者

    • LEE Je-Hoom
    • Division of Electronics and Information Communication Engineering, Kangwon National University
    • SONG Young-Jun
    • the Chungbuk BIT Research-Oriented University Consortium, Chungbuk National University
    • KIM Sang-Choon
    • Division of Electronics and Information Communication Engineering, Kangwon National University

抄録

This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 94(8), 1547-1556, 2011-08-01

    一般社団法人 電子情報通信学会

参考文献:  13件中 1-13件 を表示

各種コード

  • NII論文ID(NAID)
    10030192408
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  J-STAGE 
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