A Leakage Efficient Instruction TLB Design for Embedded Processors

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著者

    • LEI Zhao
    • the Faculty of Science and Technology, Keio University
    • XU Hui
    • the Faculty of Science and Technology, Keio University
    • SUNATA Tetsuya
    • the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology
    • NAMIKI Mitaro
    • the Department of Computer and Information Sciences, Tokyo University of Agriculture and Technology

抄録

This paper presents a leakage-efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 94(8), 1565-1574, 2011-08-01

    The Institute of Electronics, Information and Communication Engineers

参考文献:  17件中 1-17件 を表示

各種コード

  • NII論文ID(NAID)
    10030192443
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  J-STAGE 
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