Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

• KUMAKI Takeshi

  Department of VLSI System Design, Ritsumeikan University

• KOIDE Tetsushi

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

• MATTAUSCH Hans Jürgen

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

• TAGAMI Masaharu

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

• ISHIZAKI Masakatsu

  Research Institute for Nanodevice and Bio Systems, Hiroshima University

Abstract

This paper presents a software-based parallel cryptographic solution with a massive-parallel memory-embedded SIMD matrix (MTX) for data-storage systems. MTX can have up to 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. Furthermore, a next-generation SIMD matrix called MX-2 has been developed by expanding processing-element capability of MTX from 2-bit to 4-bit processing. These SIMD matrix architectures are verified to be a better alternative for processing repeated-arithmetic and logical-operations in multimedia applications with low power consumption. Moreover, we have proposed combining Content Addressable Memory (CAM) technology with the massive-parallel memory-embedded SIMD matrix architecture to enable fast pipelined table-lookup coding. Since both arithmetic logical operation and table-lookup coding execute extremely fast on these architectures, efficient execution of encryption and decryption algorithms can be realized. Evaluation results of the CAM-less and CAM-enhanced massive-parallel SIMD matrix processor for the example of the Advanced Encryption Standard (AES), which is a widely-used cryptographic algorithm, show that a throughput of up to 2.19Gbps becomes possible. This means that several standard data-storage transfer specifications, such as SD, CF (Compact Flash), USB (Universal Serial Bus) and SATA (Serial Advanced Technology Attachment) can be covered. Consequently, the massive-parallel SIMD matrix architecture is very suitable for private information protection in several data-storage media. A further advantage of the software based solution is the flexible update possibility of the implemented-cryptographic algorithm to a safer future algorithm. The massive-parallel memory-embedded SIMD matrix architecture (MTX and MX-2) is therefore a promising solution for integrated realization of real-time cryptographic algorithms with low power dissipation and small Si-area consumption.

Journal

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E94-D (9), 1742-1754, 2011

  The Institute of Electronics, Information and Communication Engineers

Keywords

• matrix-processing architecture
• SIMD
• bit-serial and word-parallel
• CAM
• table-lookup coding
• cryptographic algorithm
• AES

Details

• CRID: 1390282679356435072
• NII Article ID: 10030192810
• NII Book ID: AA10826272
• DOI: 10.1587/transinf.e94.d.1742
• ISSN: 17451361
• ISSN: 09168532
• Web Site: http://www.jstage.jst.go.jp/article/transinf/E94.D/9/E94.D_9_1742/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed