FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic

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著者

    • LEI Yuanwu
    • National Laboratory for Parallel and Distribution Processing, National University of Defense Technology
    • DOU Yong
    • National Laboratory for Parallel and Distribution Processing, National University of Defense Technology
    • ZHOU Jie
    • National Laboratory for Parallel and Distribution Processing, National University of Defense Technology

抄録

Many scientific applications require efficient variable-precision floating-point arithmetic. This paper presents a special-purpose Very Large Instruction Word (VLIW) architecture for variable precision floating-point arithmetic (VV-Processor) on FPGA. The proposed processor uses a unified hardware structure, equipped with multiple custom variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved through the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. We take division and exponential function as examples to illustrate the design of variable-precision elementary algorithms in VV-Processor. Finally, we create a prototype of VV-Processor unit on a Xilinx XC6VLX760-2FF1760 FPGA chip. The experimental results show that one VV-Processor unit, running at 253MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93GHz by a factor of 5X-37X for basic variable-precision arithmetic operations and elementary functions.

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 94(11), 2173-2183, 2011-11-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030193941
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌  J-STAGE 
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