On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques
-
- CHIM Fu-Shing
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- LAM Tak-Kei
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- WU Yu-Liang
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- FAN Hongbing
- Department of Physics and Computer Science, Wilfrid Laurier University
Search this Article
Author(s)
-
- CHIM Fu-Shing
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- LAM Tak-Kei
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- WU Yu-Liang
- Department of Computer Science and Engineering, The Chinese University of Hong Kong
-
- FAN Hongbing
- Department of Physics and Computer Science, Wilfrid Laurier University
Journal
-
- IEICE transactions on fundamentals of electronics, communications and computer sciences
-
IEICE transactions on fundamentals of electronics, communications and computer sciences 94(12), 2853-2865, 2011-12-01
References: 31
-
1
- Logic synthesis system with standard GBAW patterns as building units
-
HO C. K.
International Conference on Communications, Circuits and Systems, June 2004, 1238-1242, 2004
Cited by (1)
-
2
- FPGA technology mapping optimization by rewiring algorithms
-
TANG W. C.
IEEE International Symposium on Circuits and Systems, May 2005, 5653-5656, 2005
Cited by (1)
-
3
- Further improve circuit partitioning using GBAW logic perturbation techniques
-
WU Y. L.
IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(3), 451-460, 2003
Cited by (1)
-
4
- Layout driven logic synthesis for FPGAs
-
CHANG S. C.
Proc. Design Automation Conferencep, June 1994, 308-313, 1994
Cited by (1)
-
5
- Fast placement-intact logic perturbation targeting for fpga performance improvement
-
ZHOU L.
3rd Southern Conference on Programmable Logic, 2007, 63-68, 2007
Cited by (1)
-
6
- How much can logic perturbation help from netlist to final routing for fpgas
-
ZHOU C. L.
44th ACM/IEEE Design Automation Conference, 2007, 922-927, 2007
Cited by (1)
-
7
- Single-pass reundancy addition and removal
-
CHANG C. W.
Proc. ACM/IEEE Int. Conf. Computer-Aided Design, Nov. 2001, 606-609, 2001
Cited by (1)
-
8
- A fast graph-based alternative wiring scheme for Boolean networks
-
WU Y. L.
International Conference on VLSI Design, 2000, 268-273, 2000
Cited by (1)
-
9
- On improved graph-based alternative wiring scheme for multi-level logic optimization
-
WU Y. L.
IEEE International Conference on Electronics, Circuits and Systems, Dec. 2000, 654-657, 2000
Cited by (1)
-
10
- A new enhanced SPFD rewiring algorithm
-
CONG J.
Proc. IEEE/ACM International Conference on Computer-Aided Design., Nov. 2002, 672-678, 2002
Cited by (1)
-
11
- Implementation and use of SPFDs in optimizing Boolean networks
-
SINHA S.
Proc. ACM/IEEE Int. Conf. Computer-Aided Design, Nov. 1998, 103-110, 1998
Cited by (1)
-
12
- One-pass redundancy identification and removal
-
ABRAMOVICI M.
International Test Conference, Sept. 1992, 807-815, 1992
Cited by (1)
-
13
- Improving single-pass redundancy addition and removal
-
LO W. H.
IEEE International Symposium on VLSI Design, Automation and Test, April 2006, 1-4, 2006
Cited by (1)
-
14
- Who are the alternative wires in your neighborhood (alternative wires identification without search)
-
CHANG C. W.
Great Lakes Symposium on VLSI, 2001, 103-108, 2001
Cited by (1)
-
15
- Identification of undetectable faults in combinational circuits
-
HARIHARA M.
IEEE International Conference on Computer Design, Oct. 1989, 290-293, 1989
Cited by (1)
-
16
- <no title>
-
SENTOVICH E. M.
SIS : A system for sequential circuit synthesis, 1992
Cited by (1)
-
17
- Further improve excellent graph-based fpga technology mapping by rewiring
-
TANG W. C.
Proc. International Symposium on Circuits and Systems, May 2007, 1049-1052, 2007
Cited by (1)
-
18
- DAOmap : A depth-optimal area optimization mapping algorithm for FPGA designs
-
CHAN D.
Proc. International Conference on Computered-Aided Design, Nov. 2004, 752-759, 2004
Cited by (1)
-
19
- Fpga technology mapping : A study of optimality
-
LING A.
28th ACM/IEEE Design Automation Conference, 2005, 427-432, 2005
Cited by (1)
-
20
- <no title>
-
Berkeley Logic Synthesis and Verification Group
ABC : A system for sequential synthesis and verification, release 70911
Cited by (1)
-
21
- Combinational and sequential mapping with priority cuts
-
MISHCHENKO A.
Proc. International Conference on Computer-Aided Design, Nov. 2007, 354-361, 2007
Cited by (1)
-
22
- Sat-based logic optimization and resynthesis
-
MISHCHENKO A.
Proc. IWLS'07, 358-364, 2008
Cited by (1)
-
23
- Boolean factoring and decomposition of logic networks
-
MISHCHENKO A.
Proc. 2008 IEEE/ACM International Conference on Computer-Aided Design, ICCAD'08, Piscataway, NJ, USA, 38-44, 2008
Cited by (1)
-
24
- A quantitative comparsion and analysis on rewiring techniques
-
TANG W. C.
Proc. International Conference on ASIC, Oct. 2003, 242-245, 2003
Cited by (1)
-
25
- Post-layout logic restructuring using alternative wires
-
CHANG S. C.
IEEE Trans. CAD 16(6), 587-596, 1997
DOI Cited by (5)
-
26
- Combinational and sequential logic optimization by redundancy addition and removal
-
ENTRENA L. A.
IEEE Trans. CAD 14(7), 909-916, 1995
DOI Cited by (6)
-
27
- Perturb and simplify: Multilevel Boolean network optimizer
-
CHANG S. C.
IEEE Trans. CAD 15(12), 1494-1504, 1996
DOI Cited by (5)
-
28
- Fast Boolean optimization by rewiring
-
CHANG S. C.
Proc. Int. Conf. Computer-Aided Design, Nov. 1996, 262-269, 1996
Cited by (2)
-
29
- Circuit optimization by rewiring
-
CHANG S. C.
IEEE Trans. Comput. 48(9), 962-969, 1999
DOI Cited by (3)
-
30
- FIRE : A faultindependent combinational redundancy identification algorithm
-
IYER M.
IEEE Trans. VLSI Systems, 295-301, 1996
Cited by (7)
-
31
- Optimality study of logic synthesis for lut-based fpgas
-
CONG J.
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 26(2), 230-239, 2007
Cited by (1)