A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones

• MONDAL Md. Nazrul Islam

  Department of Information Engineering, Hiroshima University

• NAKANO Koji

  Department of Information Engineering, Hiroshima University

• ITO Yasuaki

  Department of Information Engineering, Hiroshima University

抄録

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous ROMs into an equivalent circuit with synchronous ones. The resulting circuit with synchronous ROMs can be embedded into FPGAs. We also discuss several techniques to decrease the latency and increase the clock frequency of the resulting circuits.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E94-D (12), 2378-2388, 2011

  一般社団法人 電子情報通信学会

キーワード

• FPGA
• block RAMs
• asynchronous read operations
• rewriting algorithm

詳細情報

• CRID: 1390282679355934080
• NII論文ID: 10030538006
• NII書誌ID: AA10826272
• DOI: 10.1587/transinf.e94.d.2378
• ISSN: 17451361
• ISSN: 09168532
• Web Site: http://ir.lib.hiroshima-u.ac.jp/00033775
• Web Site: http://www.jstage.jst.go.jp/article/transinf/E94.D/12/E94.D_12_2378/_pdf
• 本文言語コード: en
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