A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
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- JOZWIK Krzysztof
- Graduate School of Information Science, Nagoya University
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- TOMIYAMA Hiroyuki
- College of Science and Engineering, Ritsumeikan University
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- HONDA Shinya
- Graduate School of Information Science, Nagoya University
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- TAKADA Hiroaki
- Graduate School of Information Science, Nagoya University
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Abstract
Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E95-D (2), 345-353, 2012
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390001204379173504
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- NII Article ID
- 10030610564
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- NII Book ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed