A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition

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This paper presents a memory-efficient VLSI architecture for output probability computations (OPCs) of continuous hidden Markov models (HMMs) and likelihood score computations (LSCs). These computations are the most time consuming part of HMM-based isolated word recognition systems. We demonstrate multiple fast store-based block parallel processing (MultipleFastStoreBPP) for OPCs and LSCs and present a VLSI architecture that supports it. Compared with conventional fast store-based block parallel processing (FastStoreBPP) and stream-based block parallel processing (StreamBPP) architectures, the proposed architecture requires fewer registers and less processing time. The processing elements (PEs) used in the FastStoreBPP and StreamBPP architectures are identical to those used in the MultipleFastStoreBPP architecture. From a VLSI architectural viewpoint, a comparison shows that the proposed architecture is an improvement over the others, through efficient use of PEs and registers for storing input feature vectors.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 456-467, 2012-04-01

    The Institute of Electronics, Information and Communication Engineers

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各種コード

  • NII論文ID(NAID)
    10030940566
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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