A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
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- NAKATA Yohei
- Kobe University
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- KAWAGUCHI Hiroshi
- Kobe University
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- YOSHIMOTO Masahiko
- Kobe University JST CREST
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抄録
As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E95.C (4), 523-533, 2012
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001204379585536
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- NII論文ID
- 10030940680
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- NII書誌ID
- AA10826283
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- BIBCODE
- 2012IEITE..95..523N
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- ISSN
- 17451353
- 09168524
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- HANDLE
- 20.500.14094/90002971
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- IRDB
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- 使用不可