0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

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It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as <i>V</i><sub>DD</sub> is reduced, a boosted word-voltage scheme is first proposed. Second, <i>V</i><sub>t</sub> variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and <i>V</i><sub>t</sub> variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 555-563, 2012-04-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030940752
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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