0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

• KOTABE Akira

  Central Research Laboratory, Hitachi, Ltd.

• ITOH Kiyoo

  Central Research Laboratory, Hitachi, Ltd.

• TAKEMURA Riichiro

  Central Research Laboratory, Hitachi, Ltd.

Abstract

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as V_DD is reduced, a boosted word-voltage scheme is first proposed. Second, V_t variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and V_t variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E95.C (4), 555-563, 2012

  The Institute of Electronics, Information and Communication Engineers

Keywords

• 0.5-V 25-nm 6-T SRAM cell
• boosted word voltage
• FD-MOSFETs
• repair
• worst design

Details

• CRID: 1390001204379532160
• NII Article ID: 10030940752
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e95.c.555
• BIBCODE: 2012IEITE..95..555K
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E95.C/4/E95.C_4_555/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed