Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor

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Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 564-571, 2012-04-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030940776
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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