A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

• YOSHIMOTO Shusuke

  Kobe University

• TERADA Masaharu

  Kobe University

• OKUMURA Shunsuke

  Kobe University

• SUZUKI Toshikazu

  Semiconductor Technology Academic Research Center (STARC)

• MIYANO Shinji

  Semiconductor Technology Academic Research Center (STARC)

• KAWAGUCHI Hiroshi

  Kobe University

• YOSHIMOTO Masahiko

  JST, CREST

Abstract

This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - V_tn and therefore saves the active power in the half-selected columns (where V_tn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125°C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the V_tn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-µW/MHz writing energy and 72.8-µW leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 µW/MHz (12.9 pJ/access) at a supply voltage of 0.5V and operating frequency of 6.25MHz in a 50%-read/50%-write operation.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E95.C (4), 572-578, 2012

  The Institute of Electronics, Information and Communication Engineers

Keywords

• SRAM
• 8T
• low energy
• disturb
• half select
• write back

Details

• CRID: 1390001204379529856
• NII Article ID: 10030940790
• NII Article ID: 120005672405
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e95.c.572
• BIBCODE: 2012IEITE..95..572Y
• ISSN: 17451353
• ISSN: 09168524
• HANDLE: 20.500.14094/90002972
• Web Site: https://www.jstage.jst.go.jp/article/transele/E95.C/4/E95.C_4_572/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • IRDB
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed