A 40-nm 0.5-V 20.1-μW/MHz 8T SRAM with low-energy disturb mitigation scheme

• YOSHIMOTO S.

Journal

• Digest of Technical Papers 2011 Symposium on VLSI Circuits, June 2011

  Digest of Technical Papers 2011 Symposium on VLSI Circuits, June 2011 72-73, 2011

Details

• CRID: 1572261550675747328
• NII Article ID: 10030940791
• Data Source:
  • CiNii Articles