Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

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A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-<i>V</i><sub>T</sub> PMOS amplifier and a low-<i>V</i><sub>T</sub> NMOS amplifier which is composed of high-<i>V</i><sub>T</sub> NMOSs and a low-<i>V</i><sub>T</sub> cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-<i>V</i><sub>T</sub> CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6ns and a writing time of 0.6ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13ns. The gate level control of the high-<i>V</i><sub>T</sub> NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 594-599, 2012-04-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030940831
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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