Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations

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抄録

This paper presents design of a novel high speed booth encoder-decoder in a 0.35µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 706-709, 2012-04-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030940995
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    SHO
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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