Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations
This paper presents design of a novel high speed booth encoder-decoder in a 0.35µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.
- IEICE transactions on electronics
IEICE transactions on electronics 95(4), 706-709, 2012-04-01