A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

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A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35µm CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(4), 710-712, 2012-04-01

    The Institute of Electronics, Information and Communication Engineers

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各種コード

  • NII論文ID(NAID)
    10030941001
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    SHO
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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