The Effect of Device Layout Schemes on RF Performance of Multi-Finger MOSFETs

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In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (<i>C<sup>e</sup><sub>gs</sub></i>, <i>C<sup>e</sup><sub>gd</sub></i>) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (<i>f<sub>T</sub></i>) and maximum oscillation frequency (<i>f<sub>max</sub></i>) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers <i>N<sub>f</sub></i> on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, <i>f<sub>T</sub></i> is slightly degraded but <i>f<sub>max</sub></i> is significantly improved, especially for larger <i>N<sub>f</sub></i>, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.

収録刊行物

  • IEICE transactions on electronics

    IEICE transactions on electronics 95(5), 785-791, 2012-05-01

    一般社団法人 電子情報通信学会

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各種コード

  • NII論文ID(NAID)
    10030941215
  • NII書誌ID(NCID)
    AA10826283
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168524
  • データ提供元
    CJP書誌  J-STAGE 
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