Source/Drain Engineering for High Performance Vertical MOSFET




    • IMAMOTO Takuya
    • Center for Interdisciplinary Research, Tohoku University, JST-CREST
    • ENDOH Tetsuo
    • Center for Interdisciplinary Research, Tohoku University, JST-CREST


In this paper, Source/Drain (<i>S/i>/<i>D</i>) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual <i>S/i>/<i>D</i> profile while degradation of driving current (<i>I<sub>ON</sub></i>) due to the parasitic series resistance (<i>R<sub>para</sub></i>) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (<i>SS</i>), <i>I<sub>ON</sub></i>, and <i>R<sub>para</sub></i>, S/D engineering is investigated. The dependency of device performance on S/D abruptness (<i>σ</i><sub>S/D</sub>) for various Lightly Doped Drain Extension (LDD) abruptness (<i>σ<sub>LDD</sub></i>) is analyzed. In this study, Spacer Length (<i>L<sub>SP</sub></i>) is defined as a function of <i>σ</i><sub>S/D</sub>. As <i>σ</i><sub>S/D</sub> becomes smaller and S/D becomes more abrupt, <i>L<sub>SP</sub></i> becomes shorter. <i>SS</i> depends on the <i>σ</i><sub>S/D</sub> rather than the <i>σ<sub>LDD</sub></i>. <i>I<sub>ON</sub></i> has the peak value of 1750µA/µm at <i>σ</i><sub>S/D</sub> =2nm/dec. and <i>σ<sub>LDD</sub></i>=3nm/dec. when the silicon pillar diameter (<i>D</i>) is 30nm and the gate length (<i>Lg</i>) is 60nm. As <i>σ</i><sub>S/D</sub> becomes small, higher <i>I<sub>ON</sub></i> is obtained due to reduction of <i>R<sub>para</sub></i> while <i>SS</i> is degraded. However, when <i>σ</i><sub>S/D</sub> becomes too small in the short channel devices (<i>Lg</i> =60nm and <i>Lg</i> =45nm), <i>I<sub>ON</sub></i> is degraded because the leakage current due to GIDL is increased and reaches <i>I<sub>OFF</sub></i> limit of 100nA/µm. In addition, as <i>σ<sub>LDD</sub></i> becomes larger, larger <i>I<sub>ON</sub></i> is obtained in the case of <i>Lg</i> =100nm and <i>Lg</i> =60nm because channel length becomes shorter. On the other hand, in the case of <i>Lg</i> =45nm, as <i>σ<sub>LDD</sub></i> becomes larger, <i>I<sub>ON</sub></i> is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on <i>D</i> is investigated. By slimming <i>D</i> from 30nm to 10nm, while <i>SS</i> is improved and approaches the ideal value of 60mV/Decade, <i>I<sub>ON</sub></i> is degraded due to increase of on-resistance (<i>R<sub>on</sub></i>). From these results, it is necessary to reduce <i>R<sub>para</sub></i> while <i>I<sub>OFF</sub></i> meets limit of 100nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the <i>R<sub>para</sub></i> and GIDL on <i>I<sub>ON</sub></i> becomes more significant, and therefore, the trade-off between <i>σ</i><sub>S/D</sub> and <i>I<sub>ON</sub></i> has a much greater impact on S/D engineering of V-MOSFET.


  • IEICE transactions on electronics

    IEICE transactions on electronics 95(5), 807-813, 2012-05-01

    一般社団法人 電子情報通信学会

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