Reduction of Base-Collector Capacitance in InP/InGaAs DHBT with Buried SiO₂ Wires

• TAKEBE Naoaki

  Department of Physical Electronics, Tokyo Institute of Technology

• MIYAMOTO Yasuyuki

  Department of Physical Electronics, Tokyo Institute of Technology

Abstract

In this paper, we report the reduction in the base-collector capacitance (C_BC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO₂ wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the C_BC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO₂ wires by adjusting the growth temperature, and a reduction in C_BC with buried SiO₂ wires was confirmed. The estimated C_BC of the BG-HBT was 7.6fF, while that of the conventional HBT was 8.6fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E95.C (5), 917-920, 2012

  The Institute of Electronics, Information and Communication Engineers

Keywords

• heterojunction bipolar transistor
• InP
• base-collector capacitance
• in situ etching

Details

• CRID: 1390282679354503936
• NII Article ID: 10030941590
• NII Article ID: 130002135544
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e95.c.917
• BIBCODE: 2012IEITE..95..917T
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E95.C/5/E95.C_5_917/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed