Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

• YOSHIMOTO Shusuke

  Kobe University

• AMASHITA Takuro

  Kobe University

• OKUMURA Shunsuke

  Kobe University

• NII Koji

  Renesas Electronics Corporation

• YOSHIMOTO Masahiko

  JST, CREST

• KAWAGUCHI Hiroshi

  Kobe University

抄録

This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A (8), 1359-1365, 2012

  一般社団法人 電子情報通信学会

キーワード

• SRAM
• single-event upset (SEU)
• bit error rate (BER)
• soft error rate (SER)
• neutron particle
• alpha particle

詳細情報

• CRID: 1390282681287321216
• NII論文ID: 120005672390
• NII論文ID: 10031126654
• NII書誌ID: AA10826239
• DOI: 10.1587/transfun.e95.a.1359
• BIBCODE: 2012IEITF..95.1359Y
• ISSN: 17451337
• ISSN: 09168508
• HANDLE: 20.500.14094/90002974
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E95.A/8/E95.A_1359/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • IRDB
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可