A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65nm CMOS
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- LEE Sangyeop
- Solutions Research Laboratory, Tokyo Institute of Technology
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- KANEMARU Norifumi
- Solutions Research Laboratory, Tokyo Institute of Technology
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- IKEDA Sho
- Solutions Research Laboratory, Tokyo Institute of Technology
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- KAMIMURA Tatsuya
- Solutions Research Laboratory, Tokyo Institute of Technology
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- TANOI Satoru
- Solutions Research Laboratory, Tokyo Institute of Technology
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- ITO Hiroyuki
- Solutions Research Laboratory, Tokyo Institute of Technology
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- ISHIHARA Noboru
- Solutions Research Laboratory, Tokyo Institute of Technology
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- MASU Kazuya
- Solutions Research Laboratory, Tokyo Institute of Technology
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抄録
This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34GHz with reference signals of 528MHz was -119dBc/Hz.
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E95.C (10), 1589-1597, 2012-10-01
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001204378764800
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- NII論文ID
- 10031142794
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- NII書誌ID
- AA10826283
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- ISSN
- 17451353
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- JaLC
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- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可