A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

• OKUMURA Shunsuke

  Kobe University

• YOSHIMOTO Shusuke

  Kobe University

• KAWAGUCHI Hiroshi

  Kobe University

• YOSHIMOTO Masahiko

  Kobe University JST CREST

抄録

We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1×10^-12.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A (12), 2226-2233, 2012

  一般社団法人 電子情報通信学会

キーワード

• SRAM
• chip ID
• physical unclonable function (PUF)

詳細情報

• CRID: 1390282681288902016
• NII論文ID: 10031161356
• NII論文ID: 120005672415
• NII書誌ID: AA10826239
• DOI: 10.1587/transfun.e95.a.2226
• ISSN: 17451337
• ISSN: 09168508
• HANDLE: 20.500.14094/90002976
• Web Site: https://www.jstage.jst.go.jp/article/transfun/E95.A/12/E95.A_2226/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • IRDB
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可