Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

• HIRAMATSU Yoshitaka

  Central Research Laboratory, Hitachi, Ltd.

• WAIDYASOORIYA Hasitha Muthumala

  Graduate School of Information Sciences, Tohoku University

• HARIYAMA Masanori

  Graduate School of Information Sciences, Tohoku University

• NOJIRI Toru

  Central Research Laboratory, Hitachi, Ltd.

• UCHIYAMA Kunio

  Central Research Laboratory, Hitachi, Ltd.

• KAMEYAMA Michitaka

  Graduate School of Information Sciences, Tohoku University

Abstract

The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16×16 pixel blocks.

Journal

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E95.C (12), 1872-1882, 2012

  The Institute of Electronics, Information and Communication Engineers

Keywords

• block matching
• heterogeneous multi-core
• dynamically reconfigurable processor
• data transfer
• accelerator

Details

• CRID: 1390282679356584704
• NII Article ID: 10031161435
• NII Book ID: AA10826283
• DOI: 10.1587/transele.e95.c.1872
• ISSN: 17451353
• ISSN: 09168524
• Web Site: https://www.jstage.jst.go.jp/article/transele/E95.C/12/E95.C_1872/_pdf
• Text Lang: en
• Data Source:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• Abstract License Flag: Disallowed